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KS86C4302/c4304/p4304 product overview 1 - 1 1 product overview sam87r i product family samsung's sam87ri family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a address/data bus architecture and a large number of bit- configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. KS86C4302/c4304 microcontroller the KS86C4302/c4304 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam87ri cpu core. the KS86C4302/c4304 is a versatile microcontroller , with its a/d converter, timer, pwm, and sio it can be used in a wide range of general purpose applications. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the KS86C4302/c4304 ha ve 2-kbytes or 4 - kbytes of program memory on-chip (rom) and 112-bytes of general purpose register area ram . using the sam87ri design approach, the following peripherals were integrated with the sam87ri core: ? three configurable i/o ports (13 pins) ? five interrupt s ources with one vector and one interrupt level ? one 8-bit timer/counter with time interval mode ? analog to digital converter with five input channels and 10-bit resolution ? one synchronous sio module ? one 12-bit pwm output the KS86C4302/c4304 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer/counter, pwm, adc, and sio. KS86C4302/c4304 is available in a 20/18/16- pin dip and a 20-pin sop package. otp the ks86p4304 is an otp (one time programmable) version of the KS86C4302/c4304 microcontroller. the ks86p4304 has on-chip 4-kbyte one-time-programmable eprom instead of masked rom. the ks86p4304 is fully compatible with the KS86C4302/c4304, in function, in d.c. electrical characteristics and in pin configuration.
product overview KS86C4302/c4304/p4 304 1 - 2 features cpu ? sam87r i cpu core memory ? 2/ 4-kbyte internal program memory (rom) ? 112 -byte general purpose register area (ram) instruction set ? 41 instructions ? the sam87ri core provides all the sam87 core instruction except the word-oriented instruction, multiplication, division, and some one-byte instruction. instruction execution time ? 600 n s at 10 mhz f osc (minimum cycles) ? 375 n s at 16 mhz f osc (minimum cycles) interrupts ? 5 interrupt sources with one vector and o ne level interrupt structure general i/o ? two i/o ports ( toatal 13 pins ) ? one output only port (port 2) ? bit programmable ports serial i/o ? one synchronius serial i/o module ? selectable transmit and receive rates built-in reset circuit (lvd) ? low voltage detector for safe reset timer/counter s ? one 8-bit ba sic timer for watchdog function ? one 8- bit timer/counter for the time interval mode pwm module ? 12-bit pwm 1-ch (max: 250 khz) ? 6-bit base + 6-bit extension frame a/d converter ? five analog input pins ? 10-bit conversion resolution buzzer frequency range ? 200 hz to 20 khz signal can be generated oscillation frequency ? 1 mhz to 16 mhz external crystal oscillator ? maximum 16 mhz cpu clock ? 4 mhz rc oscillator operating temperature range ? - 4 0 c to + 85 c operating voltage range ? 3.0 v to 5.5 v otp interface protocol spec ? serial otp package types ? 2 0-pin dip -300 ? 20-pin sop-375 ? 18-pin dip-300 ? 16-pin dip-300
KS86C4302/c4304/p4304 product overview 1 - 3 block diagram sam87ri cpu p0.0-p0.3 buz, pwm, int0, int1 i/o port and interrupt control 2-kb rom 4-kb rom 112-byte register file port 0 port 1 p1.0-p1.4 adc0-adc4 sck, so, si, clo port 2 sio timer 0 buz adc pwm osc basic timer p2.0/sck p2.1/so p2.2 p2.3 sck (p1.3 or p2.0) so (p1.2 or p2.1) si (p1.1) x in x out p0.2/t0ck p0.0/buz adc0-adc4 p0.1/pwm figure 1 -1 . block diagram
product overview KS86C4302/c4304/p4 304 1 - 4 pin assignments KS86C4302/ 4304 (top view) v dd p0.3/int1 p1.0/adc0 p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so p2.3 20 19 18 17 16 15 14 13 12 11 v ss x in x out test p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz p2.0/sck p2.2 1 2 3 4 5 6 7 8 9 10 figure 1 -2 . pin assignment diagram ( 20 -pin dip package)
KS86C4302/c4304/p4304 product overview 1 - 5 KS86C4302/ 4304 (top view) v dd p0.3/int1 p1.0/adc0 p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so p2.3 20 19 18 17 16 15 14 13 12 11 v ss x in x out test p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz p2.0/sck p2.2 1 2 3 4 5 6 7 8 9 10 figure 1 -3 . pin assignment diagram ( 20 -pin sop package)
product overview KS86C4302/c4304/p4 304 1 - 6 KS86C4302/ 4304 (top view) v dd p0.3/int1 p1.0/adc0 p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so 18 17 16 15 14 13 12 11 10 v ss x in x out test p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz p2.0/sck 1 2 3 4 5 6 7 8 9 figure 1 -4 . pin assignment diagram ( 18 -pin dip package) v ss x in x out test p0.2/t0ck/int0 p0.1/pwm reset p0.0/buz KS86C4302/ 4304 (top view) v dd p0.3/int1 p1.0/adc0 p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 figure 1-5. pin assignment diagram (16-pin dip package)
KS86C4302/c4304/p4304 product overview 1 - 7 pin descriptions table 1 - 1. KS86C4302/c4304 pin descriptions pin names pin type pin description circuit type share pins p0.0-p0. 3 i/o bit-programmable i/o port for schmitt trigger input or push-pull, open-drain output. pull-up resistors are assignable by software. port 0 pins can also be used as alternative function. e buz pwm int0/t0ck int1 p1.0-p1.4 i/o bit-programmable i/o port for schmitt trigger input or push-pull , open-drain output. pull-up resistors are assignable by software. port 1 pins can also be used as alternative function. e-1 adc0-adc4 si so sck clo p2.0-p2.3 o p ush-pull or open-drain output port. pull up resistors are assignable by software. port 2 .0-2.1 pins can also be used as alternative function. e-2 sck so x in , x out ? crystal/ceramic, or rc oscillator signal for system clock. ? ? reset i system reset signal input pin. b ? test i test signal input pin (for factory use only: must be connected to v ss ) ? ? v dd , v ss ? voltage input pin and ground ? ? av ref ? a/d converter reference voltage input and ground ? ? a v ss bonded to v ss internally sck i/o serial interface clock i/o e-1 e-2 p1.3 or p2.0 so o serial data output e-1 e-2 p1.2 or p2.1 si i serial data input e-1 p1.1 clo o system clock output port e-1 p1.4 buz o 200 hz- 20 khz frequency output for buzzer sound e p0.0 pwm o 12-bit pwm output e p0.1 int 0-int1 i external interrupt input port e p0.2 p0.3 t0ck i timer 0 external clock input e p0.2 adc0-adc4 i a/d converter input e-1 p1.0-p1.4
product overview KS86C4302/c4304/p4 304 1 - 8 pin circuits p-channel n-channel in v dd figure 1 -6 . pin circuit type a in v dd pull-up resistor figure 1 -7 . pin circuit type b p-channel n-channel v dd out output disable data figure 1 -8 . pin circuit type c i/o output disable data circuit type c pull-up enable v dd data p-channel figure 1 -9 . pin circuit typ e d
KS86C4302/c4304/p4304 product overview 1 - 9 n-ch v dd p-ch output disable output data open-drain input pull-up enable v dd i/o pull-up resistor figure 1 -10 . pin circuit type e analog input n-ch v dd p-ch output disable output data open-drain digital input pull-up enable v dd i/o pull-up resistor figure 1 -11 . pin circuit type e-1 n-ch v dd p-ch output disable output data open-drain pull-up enable v dd i/o pull-up resistor figure 1 -12 . pin circuit type e-2
product overview KS86C4302/c4304/p4 304 1 - 10 notes
KS86C4302/c4304/p4304 electrical data 1 4- 1 1 4 electrical data overview in this section, the following KS86C4302/c4304 electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characteristics ? a.c. electrical characteristics ? input timing measurement points ? oscillator characteristics ? oscillation stabilization time ? operating voltage range ? schmitt trigger input characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? a/d converter electrical characteristics ? lvd circuit characteristics ? lvd reset timing ? serial i/o timing characteristics ? serial data transfer timing
electrical data KS86C4302/c4304/p4 304 1 4- 2 table 14- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? - 0.3 to + 6.5 v input voltage v i all input ports - 0.3 to v dd + 0.3 v output v oltage v o all output ports - 0.3 to v dd + 0.3 v output c urrent high i oh one i/o pin active - 25 ma all i/o pins active - 80 output current l ow i ol one i/o pin active + 30 ma all i/o pins active + 1 5 0 operating temperature t a ? - 40 to + 85 c storage temperature t stg ? - 65 to + 150 c table 14- 2. dc electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit input high v oltage v i h1 ports 0, 1, and reset v dd = 3.0 to 5.5 v 0. 8 v dd ? v dd v v i h2 x in and x out v dd - 0.1 input low v oltage v i l1 ports 0, 1, and reset v dd = 3.0 to 5.5 v ? ? 0.2 v dd v v i l2 x in and x out 0.1 out put high v oltage v oh i oh = - 1 0 m a ports 0, 1, 2 v dd = 4.5 to 5.5 v v dd - 1. 5 v dd - 0.4 ? v output low v oltage v o l i o l = 25 m a port 0, 1, and 2 v dd = 4. 5 to 5.5 v ? 0.4 2.0 v
KS86C4302/c4304/p4304 electrical data 1 4- 3 table 14- 2. dc electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit input h igh l eakage current i lih1 all input s except i lih2 v in = v dd ? ? 1 ua i lih2 x in , x out v in = v dd 20 input l ow l eakage current i lil1 all inputs except i lil2 and reset v in = 0 v ? ? - 1 ua i lil2 x in , x out v in = 0 v - 20 output h igh l eakage c urrent i loh all outputs v out = v dd ? ? 2 ua output l ow l eakage c urrent i lol all outputs v out = 0 v ? ? - 2 ua pull-up r esistors r p v in = 0 v ports 0 -2 v dd = 5 v 30 47 70 k w v dd = 5 v 100 200 350 supply c urren t i dd1 run mode 16 mhz cpu clock v dd = 5v 10% ? 11 20 ma 8 mhz cpu clock v dd = 3.3 v 3 6 i dd2 idle mode 1 6 mhz cpu clock v dd = 5v 10% ? 5 8 8 mhz cpu clock v dd = 3.3 v 0.7 2.5 i dd3 stop mode v dd = 5v 10% ? 65 100 ua v dd = 3.3 v 45 80 note: d.c electrical values for supply current (i dd , to i dd3 ) do not include current drawn through internal pull-up resisters, output port drive current and adc module.
electrical data KS86C4302/c4304/p4 304 1 4- 4 table 14- 3. ac electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl int0, int1 v dd = 5v 10% ? 200 ? ns input l ow width t rsl input v dd = 5v 10% ? 1 ? us 0.8 v dd 0.2 v dd t intl t inth t rsl figure 14-1 . input timing measurement points
KS86C4302/c4304/p4304 electrical data 1 4- 5 table 14-4 . oscillator characteristics (t a = - 40 c to + 85 c) oscillator clock circuit test condition min typ max unit main crystal or ceramic x in c1 c2 x out v dd = 4. 5 to 5.5 v v dd = 3.0 to 4.5 v 1 1 ? ? 16 8 mhz external clock x in x out v dd = 4. 5 to 5.5 v v dd = 3.0 to 4.5 v 1 1 ? ? 16 8 rc oscillator x in x out r v dd = 5 v , r = 10 k w v dd = 3 v, r = 22 k w ? ? 4 2 ? ? table 14-5 . oscillation stabilization time (t a = - 40 c to + 85 c, v dd = 3.0 v to 5.5 v) oscillator test condition min typ max unit main crystal f osc > 1.0 mhz ? ? 20 ms main ceramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 10 external clock (main system) x in input high and low width (t xh , t xl ) 25 ? 500 ns oscillator stabilization t wait when released by a reset (1) ? 2 1 6 /f osc ? ms wait time t wait when released by an interrupt (2) ? ? ? notes : 1 . f osc is the oscillator frequency. 2 . the duration of the oscillator stabilization wait time, t wait , when it is released by an interrupt is dete r mined by the setting s in the basic timer control register, btcon.
electrical data KS86C4302/c4304/p4 304 1 4- 6 cpu clock 16mhz 8mhz 4mhz 3mhz 2mhz 1mhz 1 2 3 4 5 6 7 2.7 5.5 supply voltage (v) figure 14-2 . operating voltage range 0.3 v dd a = 0.2 v dd b = 0.4 v dd c = 0.6 v dd d = 0.8 v dd v out a 0.7 v dd v dd v ss b c d v in figure 14-3 . schmitt trigger input characteristics diagram
KS86C4302/c4304/p4304 electrical data 1 4- 7 table 14-6 . data retention supply voltage in stop mode (t a = ? 40 c to + 85 c , v dd = 3.0 v to 5.5 v ) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2.0 ? 5.5 v data retention supply current i dddr stop mode; v dddr = 2.0 v ? 0.1 5 ua note: supply current does not include current drawn through internal pull-up resistors or external output current loads. reset data retention mode ~ ~ ~ v dddr execution of stop instrction v dd normal operating mode oscillation stabilization time ~ stop mode reset occurs t wait note: t wait is the same as 4096 x 16 x 1/fosc 0.8 v dd 0.2 v dd figure 14-4 . stop mode release timing when initiated by a reset
electrical data KS86C4302/c4304/p4 304 1 4- 8 table 14-7. a/d converter electrical characteristics (t a = - 40 c to + 85 c , v dd = 3.0 v to 5.5 v, v ss = 0 v ) parameter symbol test conditions min typ max unit total accuracy ? v dd = 5.12 v cpu clock = 10 mhz av ref = 5.12 v av ss = 0 v ? ? 3 lsb integral linearity error ile ? ? ? 2 differential linearity error dle ? ? ? 1 offset error of top eot ? ? 1 3 offset error of bottom eob ? ? 1 2 conversion time (1) t con f osc = 10 mhz ? 50x4/ f osc ? m s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 ? ? m w adc reference voltage av ref ? 3.0 ? v dd v adc reference ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v ? ? 10 m a analog block current (2) i adc av ref = v dd = 5 v conversion time = 20 m s 1 3 ma av ref = v dd = 3 v conversion time = 20 m s 0.5 1.5 ma av ref = v dd = 5 v when power down mode 100 500 na notes: 1. ?conversion time? is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion.
KS86C4302/c4304/p4304 electrical data 1 4- 9 table 14-8 . lvd circuit characteristics (t a = - 40 c to + 85 c , v dd = 3.0 v to 5.5v ) parameter symbol conditions min typ max unit power-on reset voltage high v dd h 3.0 5.5 v power-on reset voltage low v dd l 0 2.6 3.0 v power supply voltage rise time t r 10 (note) us power supply voltage off time t off 0.5 sec power-on reset circuit i dd p r v dd = 5 v 10 % 65 100 ua consumption current v dd = 3 v 45 80 ua note: oscillation stabilization time = 2 16 / fx (= 6.55 ms at fx = 10 mhz) v dd v ddh v ddl t off t r figure 14-5. lvd reset timing
electrical data KS86C4302/c4304/p4 304 1 4- 10 table 14-9 . serial i/o timing characteristics (t a = ? 4 0 c to + 85 c, v dd = 3.0 v to 5.5 v) parameter symbol conditions min typ max unit cycle time t cky external source 1000 ? ? ns internal source 1000 high, low width t kh , t kl external source 500 ? ? internal source t kcy /2 ? 50 si setup time to low t sik external source 250 ? ? internal source 250 si hold time to high t ksi external source 400 ? ? internal source 400 output delay for to so t kso external source ? ? 300 internal source 250 note : " " means serial i/o clock frequency, " si " means serial data input, and " so " means serial data output. output data input sck t kh t kcy 0.8 v dd 0.2 v dd t kso t sik t ksi 0.8 v dd 0.2 v dd si so t kl figure 14-6 . serial data transfer timing
KS86C4302/c4304/p4304 electrical data 1 4- 11 0.0 5.0 1.0 2.0 3.0 4.0 fx = 16 mhz v dd (v) fx = 10 mhz fx = 8 mhz 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 idd1 (ma) figure 14-7. i dd1 vs v dd
electrical data KS86C4302/c4304/p4 304 1 4- 12 0.0 5.0 1.0 2.0 3.0 4.0 vol (v) 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 iol (ma) v dd = 4.5 v v dd = 5.5 v v dd = 5.0 v figure 14-8. i ol vs v ol
KS86C4302/c4304/p4304 electrical data 1 4- 13 0.0 5.0 1.0 2.0 3.0 4.0 voh (v) -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 ioh (ma) v dd = 5.5 v v dd = 5.0 v v dd = 4.5 v figure 14-9. i oh vs v oh
electrical data KS86C4302/c4304/p4 304 1 4- 14 notes
KS86C4302/c4304/p4304 mechanical data 1 5- 1 1 5 mechanical data overview the KS86C4302/c4304 is available in a 20 -pin s dip package ( samsung: 20 -dip- 3 00 a ) , a 20 -pin so p package ( samsung: 20 - sop - 375), a 18 -pin dip package ( samsung: 18 -dip- 3 00 a). package dimensions are shown in figure 1 5- 1 , 15-2, and 15-3 . note : dimensions are in millimeters. 26.80 max 26.40 0 .20 (1.77) 20-dip-300a 6.40 0 .20 #20 #1 0.46 0.10 1.52 0.10 #11 #10 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max figure 1 5- 1. 20 -dip -300a package dimensions
mechanical data KS86C4302/c4304/p4304 1 5- 2 note : dimensions are in millimeters. 20-sop-375 10.30 0 .30 #11 #20 #1 #10 13.14 max 12.74 0 .20 (0.66) 0-8 0.203 + 0.10 - 0.05 9.53 7.50 0.20 0.85 0.20 0.05 min 2.30 0.10 2.50 max 0.40 0.10 max + 0.10 - 0.05 1.27 figure 1 5-2 . 20 - sop-375 package dimensions
KS86C4302/c4304/p4304 mechanical data 1 5- 3 note : dimensions are in millimeters. 23.35 max 22.95 0 .20 (1.32) 6.40 0 .20 #18 #1 #10 #9 0-15 0.25 + 0.10 - 0.05 7.62 2.54 0.51 min 3.30 0.30 3.25 0.20 5.08 max 18-dip-300a 0.46 0.10 1.52 0.10 figure 1 5-3 . 18- dip -300a package dimensions
mechanical data KS86C4302/c4304/p4304 1 5- 4 19.80 (0.81) 6.40 #16 #1 #9 #8 0.25 7.62 2.54 1.50 0.46 0.38 3.25 3.30 5.08 figure 1 5-4 . 16- dip -300a package dimensions
KS86C4302/c4304/p4304 ks86p4304 otp 16- 1 16 ks86p4304 otp overview the ks86p4304 single-chip cmos microcontroller is the otp (one time programmable) version of the KS86C4302/c4304 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the ks86p4304 is fully compatible with the KS86C4302/c4304, in function, in d.c. electrical characteristics, and in pin configuration. because of its simple programming requirements, the ks86p4304 is ideal for use as an evaluation chip for the KS86C4302/c4304. v ss /v ss x in x out v pp / test p0.2/t0ck/int0 p0.1/pwm reset /reset p0.0/buz p2.0/sck p2.2 note: the bolds indicate an otp pin name. ks86p4304 (top view) v dd/ v dd p0.3/int1/ sclk p1.0/adc0/ sdat p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so p2.3 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 figure 16-1 . pin assignment diagram ( 20 -pin dip package)
ks86p4304 otp ks86c4 302/c4304/p4304 16- 2 ks86p4304 (top view) v dd/ v dd p0.3/int1 / sclk p1.0/adc0 / sdat p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so p2.3 20 19 18 17 16 15 14 13 12 11 v ss /v ss x in x out v pp /test p0.2/t0ck/int0 p0.1/pwm reset /reset p0.0/buz p2.0/sck p2.2 1 2 3 4 5 6 7 8 9 10 note: the bolds indicate an otp pin name. figure 1 6-2 . pin assignment diagram ( 20 -pin sop package)
KS86C4302/c4304/p4304 ks86p4304 otp 16- 3 ks86p4304 (top view) v dd/ v dd p0.3/int1/ sclk p1.0/adc0/ sdat p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref p2.1/so 18 17 16 15 14 13 12 11 10 v ss /v ss x in x out v pp /test p0.2/t0ck/int0 p0.1/pwm reset /reset p0.0/buz p2.0/sck 1 2 3 4 5 6 7 8 9 note: the bolds indicate an otp pin name. figure 1 6-3 . pin assignment diagram ( 18 -pin dip package)
ks86p4304 otp ks86c4 302/c4304/p4304 16- 4 ks86p4304 (top view) v dd/ v dd p0.3/int1/ sclk p1.0/adc0/ sdat p1.1/adc1/si p1.2/adc2/so p1.3/adc3/sck p1.4/adc4/clo av ref 16 15 14 13 12 11 10 9 v ss /v ss x in x out v pp /test p0.2/t0ck/int0 p0.1/pwm reset /reset p0.0/buz 1 2 3 4 5 6 7 8 note: the bolds indicate an otp pin name. figure 16-4. pin assingment diagram (16-pin dip package)
KS86C4302/c4304/p4304 ks86p4304 otp 16- 5 table 16-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.3 sdat 18 (20-pin) 16 (18-pin) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p0.2 sclk 19 (20-pin) 17 (18-pin) i serial clock pin (input only pin) test v pp (test) 4 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 7 i chip initialization v dd /v ss v dd /v ss 20 (20-pin), 18 (18-pin) 1 (20-pin), 1 (18-pin) i logic power supply pin. note : ( ) means the sop otp pin number. table 16-2. comparison of ks86p4304 and KS86C4302/c4304 features characteristic ks86p4304 KS86C4302/c4304 program memory 4 kbyte eprom 2k/4k byte mask rom operating voltage (v dd ) 3.0 v to 5.5 v 3.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v pin configuration 20 dip/20 sop/18 dip eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the ks86p4304, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd vpp (test) reg/ mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
ks86p4304 otp ks86c4 302/c4304/p4304 16- 6 notes

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